Documents from 1999
Server selection for mobile agent migration, Wayne Caro
Behavior synthesis for high speed 3D color interpolation using VHDL, Thomas Glanville Jr
Asynchronous circuit simulation and design methodologies, Michael Hevery
Self-Similarity in a multi-stage queueing ATM switch fabric, Adam Lange-Pearson
Investigation of a simultaneous multithreaded architecture, Marc Torrant
Documents from 1998
The Effects of the architectural design, replacement algorithm, and size parameters of cache memory in uniprocessor computer systems, Eric Berzofsky
Exploring design patterns with the Java programming language, Stephanie Burton
A Shared memory multiprocessor system architecture utilizing a uniform, Frank Casilio
Real-Time Implementation of JPEG Encoder/Decoder, Thomas M. Czyszczon, Roy S. Czernikowski, Muhammad Shaaban, and Kenneth Hsu
An Approach to remote process monitoring and control, John Dracos
Design and implementation of a DSP based MPEG-1 audio encoder, Eric Hoekstra
Evolving hardware with genetic algorithms, Kevin Kerr
Lempel Ziv Welch data compression using associative processing as an enabling technology for real time application, Manish Narang
Coarse-grained parallel genetic algorithms: Three implementations and their analysis, Daniel Pedersen
Documents from 1997
An Investigation and evaluation of promela/spin as a validation tool for asynchronous concurrent systems, Mark Bezdany
Java based location independent desktop environment, Jeffrey Harman
An Experimental analysis of the MPEG compression standard with respect to processing requirements, compression ratio, and image quality, Daniel Howard
Design and evaluation of multimedia extensions for the DLX architecture, Brian Hughes
A Morphological array image processor controller chip set, Christopher Insalaco
A Java based internet file system service, Keith Miller
The Design and modeling of input and output modules for an ATM network switch, Darin Murphy
VHDL design of a DES encryption cracking system, Thomas Oelke
Evolution of solutions to real-time problems, Greg Semeraro
Documents from 1996
A Buffering strategy for stabilizing network data rates, Brian Bell
A Petri net design, simulation, and verification tool, Richard Brink
Implementation of a real-time industrial web scanning system hardware architecture, Lowell Ferguson
A VHDL model of a superscalar implementation of the DLX instruction set architcture, Paul Ferno
Super scalar high speed 2(mew) N-well MOSIS CMOS digital halftoning processor, Anupam Gupta
VHDL implementation of an image processing chip, E. Michael Kelly
A Performance evaluation of several ATM switching architectures, Jeffrey Krieger
Boundary scan system design, Craig Loomis
The Design of a single chip 8x8 ATM switch in 0.5 micrometers CMOS VLSI, Rudi Rughoonundon
Documents from 1995
A VHDL model of a digi-neocognitron neural network for VLSI, Troy Brewster
Statistical SPICE parameter extraction for an n-well CMOS process, Scott Hildreth
ASIC design of an IIR digital filter: Using Mentor Graphics DSP Station Tools, Robert Panek
Features and neural net recognition strategies for hand printed digits, Jeffrey R. Pink
Implementation of fractal image coding, Peter Stubler
Characterization of digital film scanner systems for use with digital scene algorithms, Mark Vernacotola
Simulation of a neural network-driven fuzzy controller, Karl Ver Schneider
Documents from 1994
A Flexible development system for stepper motor based electro-mechanical subassembly design, Joseph Baco
A VHDL design of a JPEG still image compression standard decoder, Douglas Carpenter
A High speed 16-bit RISC processor chip, Wan-Fu Chen
Fuzzy approach for Arabic character recognition, Adnan El-Nasan
VHDL modeling and design of an asynchronous version of the MIPS R30000 microprocessor, Paul Fanelli
Heuristics for selecting gray scale morphological structuring elements, Paul Fetter
A Hardware approach to neural networks silicon retina, Arif K. Golwalla
Design and implementation of an asynchronous version of the MIPS R3000 microprocessor, Kevin Johnson
A Hybrid voice/text electronic mail system: an application of the integrated services digital network, Andrew McBride
Design and implementation of a real-time morphological image processor prototype, Jens Rodenberg
Documents from 1993
Reliability analysis of triple modular redundancy system with spare, Khalid A. Al-Kofahi
Simulation of a morphological image processor using VHDL - Part II: Control Mechanism, Hao Chen
Simulation of a morphological image processor using VHDL - Part I: Mathematical Components, Wei-chun Chen
A Self-timed implementation of the bi-way sorter systolic array processor, Mitchell Diamond
An Extensible, scalable microprocessor architecture, Matthew Dinmore
Design for manufacturing: Performance characterization of digital VLSI systems using a statistical analysis/inference methodology, J. Ignacio Espinosa de los Monteros
Design of a hardware efficient key generation algorithm with a VHDL implementation, James A. Goeke
Channel routing: Efficient solutions using neural networks, Taj-ul Islam
Design and implementation of an asynchronous version of the MIPS R3000 microprocessor, Scott Siers
Documents from 1992
The Design and implementation of an 8 bit CMOS microprocessor, Jeffrey Correll
A Buffer insertion priority mechanism based on the IEEE 802.4 priority scheme, Nicholas W. Oddo
Documents from 1991
Optimization algorithms for shortest path analysis, Susan M. Hojnacki
Design and simulation of a primitive RISC architecture using VHDL, Evangelos Moustakas
A Parameterized CMOS standard cell library and a full 8-bit grey scale morphological array processor, Lawrence H. Rubin
Documents from 1990
Transputer-based robot controller, Wei-Chieh Chang
Design and implementation of a systolic array to solve the Algebraic Path Problem with the specific instance of the transistive and reflexive closure of a binary relation, David Gene McCall
Documents from 1988
Design and implementation of a simulator for a local area network utilizing an IBM PC/AT or compatible computer, Christian G. Midgley
Documents from 1987
Design and implementation of a local area network utilizing Intel 310/80286 systems, James Leach
