Darin Murphy

Abstract

The purpose of this thesis is to design, model, and simulate both an input and an output module for an ATM network switch. These devices are used to interface an ATM switch with the physical protocol that is transporting data along the actual transmission medium. The I/O modules have been designed specifically to interface with the Synchronous Optical Network (SONET) protocol. This thesis studies the ATM protocol and examines the issues involved with designing an ATM I/O module chipset. A model of the design was then implemented in both C++ and \TTDL. These models were simulated in order to verify functionality and document performance. The intent of this work is to provide the background and models necessary to aid in the further study and development of entire ATM switch architectures. The input and output modules .ire onlv two functional pieces of a complete ATM switch. The software models that have been implemented by this thesis can be integrated with the other necessary functional blocks to form a complete model of a working ATM switch. These functional blocks can then be rearranged and altered to assist in the study of how different switch architectures can effect overall network performance and efficiency. The input and output modules have been designed to be as flexible as possible in order to easily adapt to future modifications.

Library of Congress Subject Headings

Asynchronous transfer mode; Telecommunication--Switching systems

Publication Date

10-1-1997

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Brown, George

Advisor/Committee Member

Shaaban, Muhammad

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK5105.35 .M87 1997

Campus

RIT – Main Campus

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