Abstract

The design, simulation and layout of a controller chip set for a morphological array image processor shall be discussed. These VLSI chips in conjunction with the Morphological Array Processor (MAP) and Arithmetic Logic Unit (ALU) chip sets perform the morphological image processing operations of erosion and dilation on 512x512 pixel, 8-bit gray scale images using a 7x7 windowing matrix in real time (60 frames per second). The controller chip set design allows for pipelining of successive MAP's as well as operation on 1024x1024 pixel, 8-bit gray scale images. To facilitate the design, additional scaleable CMOS standard library cells and corresponding parameterized schematic library components were designed and integrated with the RIT CMOS standard cell library designed by Computer Engineering graduate student Larry Rubin as part of his Masters thesis1. In particular, additional D flip-flops with both Q and Q bar outputs, and-orinverts, or-and-inverts, CMUXes, and MOSIS 64 and 84 pin pad rings were created. The cells were designed to be fabricated using the Metal Oxide Semiconductor Implementation System (MOSIS) scaleable CMOS 2.0 pm Nwell (SCN) process. A complete set of Cadence design rule verification tools were also integrated with the existing CAE tool set to perform design rule checking (DRC), electrical rule checking (ERC), layout versus schematic checking (LVS), and layout parameter extraction (LPE) for the MOSIS SCN 2.0 pm N-well dense rule set. To verify the CMOS standard cell designs, test chips were designed and sent to MOSIS for fabrication. The layout and design rule verification of the final two test chips, test chips five and six, was performed by the author. Test chip four contains a variety of MUXes and D flip-flops, test chip five contains a variety of transfer gates and inverters. The controller chip set consists of a 64 pin control chip (Controller) and an 84 pin memory controller chip (Mem_Control). The controller chips provide the ability to selectively process 512x512 or 1024x1024 image sizes by modifying the pullup or pulldown of a "size" bit. A selectable delay was implemented, through the pullup or pulldown setup of three delay bits, in the Controller to allow the Controller to be used with the single chip VLSI MAP design, the seven chip VLSI MAP design, and the Actel gate array MAP. The controller chip set allows successive MAPs to be pipelined by connecting the next Controllers pipeline start pin to the previous stages pipeline start next pin.

Library of Congress Subject Headings

Integrated circuits--Very large scale integration--Design and construction; Image processing; Morphisms (Mathematics)

Publication Date

2-1-1997

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Brown, George

Advisor/Committee Member

Pearson, Robert

Advisor/Committee Member

Czernikowski, Roy

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7874.75 .I57 1997

Campus

RIT – Main Campus

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