Description
With the immense size of images, compression has become a common way of minimizing the amount of storage necessary for images. This is also beneficial for transmission purposes. The Joint Photographic Experts Group (JPEG) standard is frequently used for still images. This standard is very flexible and many of the same algorithms can be used for video applications. Video applications require large amounts of data to be processed every second. Therefore, the following describes the hardware design of a chip allowing for high-speed compression. The design uses the JPEG algorithms and is targeted towards ASIC design. Further plans include use of field programmable gate arrays (FPGAs). The hardware design is based on grayscale images and only works with the raw image data.
Date of creation, presentation, or exhibit
1998
Document Type
Conference Paper
Department, Program, or Center
Computer Engineering (KGCOE)
Recommended Citation
Thomas M. Czyszczon, Roy S. Czernikowski, Muhammad E. Shaaban, Kenneth W. Hsu, "Real-time implementation of JPEG encoder/decoder", Proc. SPIE 3422, Input/Output and Imaging Technologies, (18 June 1998); doi: 10.1117/12.311097; https://doi.org/10.1117/12.311097
Campus
RIT – Main Campus
Comments
Copyright 1998 Society of Photo-Optical Instrumentation Engineers. One print or electronic copy may be made for personal use only. Systematic reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.
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