Abstract

Self-timed circuits with an appropriate handshake control circuit can be used to replace the global clock in a VLSI chip. By replacing the global clock many problems which face designers have disappeared along with the clock. Some of these problems are due to clock skew and capacitance scaling with smaller feature sizes. The wire capacitance cannot scale below a certain limit due to two-dimensional effects, therefore the RC delays associated with the interconnect layers do not scale proportion.ally to the feature size. The resultant increase in wire delay makes it difficult to distribute a global clock at a high frequency. This project takes an existing synchronous systolic array, the bi-way sorter, and implements the sorter algorithm using a self-timed approach. By using self-timed instead of synchronous approaches, many of the problems associated with synchronous circuits such as clock skew and large line capacitance, are avoided. In this thesis, a 2-bit, four number sorter will be designed and simulated and the advantages and drawbacks will be examined.

Library of Congress Subject Headings

Integrated circuits--Very large scale integration--Design and construction; Systolic array circuits--Design and construction

Publication Date

10-1-1993

Document Type

Thesis

Department, Program, or Center

Computer Engineering (KGCOE)

Advisor

Brown, George

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7874.75.D48 1993

Campus

RIT – Main Campus

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