Abhinav Gaur

Abstract

In the field of low power electronics, Tunnel field-effect transistors (TFETs) are gaining momentum due to aggressive voltage scaling. To enable scaling of power supply while maintaining a high Ion, a steep subthreshold slope and low I0 are required. A TFET operates as a gated PIN diode under reverse bias with the intrinsic region as the channel.

This study focuses on minimizing I0 in a III-V homojunction PIN diode. I0 or leakage current is the current owing in a PIN diode under reverse bias, that forms the o-state current (Vgate = 0 V) in a TFET. Various surface treatment combinations were performed to study surface leakage, of which, BCB and HCl were the most eective passivation and clean, respectively.

For the first time, in this study, electrical characterization of sub-micron PIN diodes was performed.

Library of Congress Subject Headings

Field-effect transistors--Design and construction; Field-effect transistors--Electric properties--Testing; Tunneling (Physics); Low voltage integrated circuits--Design and construction

Publication Date

9-25-2014

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Sean Rommel

Advisor/Committee Member

Santosh Kurinec

Advisor/Committee Member

Karl Hirschman

Comments

Physical copy available from RIT's Wallace Library at TK7871.95 .G38 2014

Campus

RIT – Main Campus

Plan Codes

MCEE-MS

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