Abstract

A CMOS process for fabricating 100 nm CMOS devices has been developed. The Leff = 100 nm NMOS and PMOS transistors are the smallest ever that have been fabricated at RIT. The process is designed with Lpoly = 0.15 µm on 150 mm (6") Silicon wafers. The NMOS and PMOS transistors are designed to operate at 1.2 V supply voltage and exhibit 0.3 V threshold voltage. 30 Å silicon-dioxide gate dielectric with Nitrous Oxide (N2O), was found to be very thin for the first lot of 100 nm devices to operate.

Individual process have been developed which include recessed oxide isolation, 30 Å gate oxide with N2O, polysilicon gate formation involving double exposure of polysilicon gate, nitride sidewall spacer formation, SALICIDE formation, precise contact cuts formation and metallization. All these individual processes have been developed and integrated into a 65 step CMOS process flow. Recipes have been developed for all process steps on variety of tools in the SMFL. The entire process has been updated on Manufacturing Execution System Application (MESA) as the ADV-CMOS 150 process which include instruction sets, specification ID's, parameter groups, and document groups making it feasible for the same process to replicated in the future.

Lots are fabricated and imperfections in the process are identified and fixed. Electrical sheet resistance results are compared to simulation results.

Library of Congress Subject Headings

Metal oxide semiconductors, Complementary--Design and construction; Nanoelectronics

Publication Date

6-2014

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Lynn F. Fuller

Advisor/Committee Member

Robert E. Pearson

Advisor/Committee Member

Ivan Puchades

Comments

Physical copy available from RIT's Wallace Library at TK7871.99.M44 P37 2014

Campus

RIT – Main Campus

Plan Codes

MCEE-MS

Download

Share

COinS