James ii Will

Abstract

An internal gettering process to collect and trap potentially harmful defects in the bulk of the silicon wafer, away from the surface where the integrated circuits are fabricated, has been developed in this work. This gettering process was then incorporated into the standard metal gate PMOS process utilized at RIT. Capacitors and diodes were electrically characterized to compare wafers that were gettered versus wafers that were not gettered. Results show that gettering did improve device characteristics, but only in the center of the wafers. The experimental results indicate that the diffusion of impurities from the furnace tube and quartz boat is competing with the gettering process during the lengthy furnace times. As a result, devices near the perimeter of the wafer exhibit poorer electrical characteristics after gettering when compared with the standards. This work shows that gettering will improve device performance, but only when accompanied by attention to furnace contamination. Gettering alone will not guarantee a better device.

Library of Congress Subject Headings

Digital integrated circuits--Design and construction; Getters; Semiconductor doping; Semiconductors--Defects; Microelectronics--Materials--Testing

Publication Date

7-1-2000

Document Type

Thesis

Department, Program, or Center

Center for Materials Science and Engineering

Advisor

Jackson, Michael

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7874.65 .W54 2000

Campus

RIT – Main Campus

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