Abstract

Thin-film electronic devices based on hydrogenated amorphous silicon (a-Si:H) or low-temperature polycrystalline silicon (LTPS) are currently utilized in the development of electro-optical systems. These systems require a transparent substrate and are commonly found in active-matrix flat-panel displays for handheld digital assistants, digital cameras, and smart phones, among other devices. The performance of these systems could be greatly enhanced in terms of speed, power consumption, resolution, and degree of integration if single-crystalline thin films became available. Corning’s Silicon-on-Glass (SiOG) technology, initially investigated prior to 2010, involved the transfer of single crystal silicon layers onto glass substrates using an anodic bonding process to create the required substrates for the fabricating of single crystal silicon thin-film transistors (TFTs). The first TFTs made at RIT with SiOG showed promising results: they operated symmetrically in NFET and PFET modes, had low subthreshold swing, and had tight VT distributions. However, when the silicon layer was bonded directly to the glass substrate, the mismatch in Young's modulus between the two materials led to the development of intrinsic defects (canyon-like voids) in the Si layer. These defects prevented devices from being scaled down to submicron sizes. Therefore, a novel thermal bonding technique incorporating a multilayer structure was used to transfer the silicon layer onto the glass wafer in order to improve the morphology of transferred single crystal silicon layer. The focus of this study was to implement the original SiOG CMOS process and to evaluate various substrate preparation methods through the electrical performance of the devices. Process variants and findings over two SiOG process lots have been documented. To demonstrate baseline device characteristics, preliminary measurements were performed on the first process lot of SiOG substrates prepared with a SiC stiffening layer, as well as the donor (mother) wafers for comparison. Significant shifting, distortion, and separation of the transfer characteristic were noted issues with Lot#1 that were resolved for Lot#2 through process modifications that significantly reduced sources of metallic contamination. However, results from Lot#2 indicate remaining issues with defects associated with the layer transfer and surface finishing processes must be addressed for needed improvements in the electrical characteristics of devices.

Library of Congress Subject Headings

Thin film transistors--Materials; Thin film transistors--Design and construction; Silicon-carbide thin films; Silicon-on-insulator technology

Publication Date

5-1-2024

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Electrical and Microelectronic Engineering, Department of

College

Kate Gleason College of Engineering

Advisor

Karl D. Hirschman

Advisor/Committee Member

Michael A. Jackson

Advisor/Committee Member

Santosh Kurinec

Comments

This thesis has been embargoed. The full-text will be available on or around 5/23/2025.

Campus

RIT – Main Campus

Plan Codes

MCEE-MS

Download

Available for download on Friday, May 23, 2025

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