There is great interest in the semiconductor industry to move to copper for advanced interconnect processing. The purpose of this study was to develop an electroplating process so further studies in copper processing can be undertaken at R.LT. Electroplating was performed using the facilities available at the University of Rochester. This system utilizes a copper sulfate based electrolyte and an 8” wafer holder. In order to use the electroplating tool for four-inch wafers, a fixture was designed. Plating was performed on Si wafers coated with adhesion and seed layer of copper at varying current densities. Plated films were characterized for sheet resistance. A 7% standard deviation in sheet resistance of the electroplated layer has been achieved with this wafer fixture design. This variation can be explained in terms of the electric field distribution in the electrolytic cell. The bulk resistivity for the plated copper was found to be 2.06E-6 ≤2•cm. Powder X-ray diffraction analysis showed that the plated films had (110) preferred orientation
Myszka, Michael T.
"Electrolytic Plating of Copper for Advanced Interconnects,"
Journal of the Microelectronic Engineering Conference: Vol. 9:
1, Article 10.
Available at: https://repository.rit.edu/ritamec/vol9/iss1/10