The concept of SFGEEPROM involves the replacement of the standard EEPROM’s floating gate with a multi-layer stacked of Silicon (Si) and Silicon Dioxide (SiO2). This multi-layer stack of Si and SiO2 is either deposited via sputtering or CVD and followed by annealing (see Figure 1). Carriers will be injected from the n+ polysilicon layer into the multi-stacked layers, and those carriers will be confined to the silicon crystallites with the thin oxide barriers between silicon layers. The distribution of charge within the stack will alter the field-effect on the underlying silicon substrate. This type of structure may result in lower operating voltage, faster write/erase cycles, the elimination of “over-erase” problems, and the utilization of only a single transistor EEPROM cell. The purpose of this experiment was to determine the feasibility of this idea and the initial results conclude that this concept works. However, more experiments and characterizations need to be done, in order to further confirm the feasibility, and determine the reliability of this device.
"Stacked Floating Gate EEPROM,"
Journal of the Microelectronic Engineering Conference: Vol. 8:
1, Article 11.
Available at: https://repository.rit.edu/ritamec/vol8/iss1/11