BF2 implanted stacked z-silicon (SAS) electrode capacitors were fabricated on n-type silicon substrates. The purpose of this electrode scheme was to quantify the effectiveness of stacked films in suppressing boron penetration into the dielectric and substrate. A 150A thick silicon dioxide was used as the capacitor dielectric. The top α-silicon electrode was deposited in a three step process using low pressure chemical vapor deposition (LPCVD). A controlled sample was fabricated using LPCVD polysilicon (Poly) as the top electrode. The samples were tested for dielectric degradation using voltage ramping techniques. The breakdown field was recorded for 2 different size capacitor areas. This testing shows that there is not significant differences between the SAS and poly gate structures on oxide quality. However, further investigation must be done on other issues such as oxide charge trapping, flat band shift and oxide growth before a complete conclusion is made.
"BF2 Implanted Stacked a-Silicon Gate Capacitors,"
Journal of the Microelectronic Engineering Conference: Vol. 7:
1, Article 6.
Available at: https://repository.rit.edu/ritamec/vol7/iss1/6