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Shallow trench isolation (STI) planarized with chemical mechanical polishing (CMP) has replaced LOCOS as the conventional isolation technique for sub-micron devices 171. The implementation and feasibility of STI has been examined for future device fabrication at RIT. STI test structures have been fabricated to investigate leakage currents between adjacent NMOS transistors in a p-substrate. Trenches were dry etched to a target depth of 2 μm to isolate n+ regions with a junction depth of 0.89 μm. Trench Refill was done with LTO planarized by chemical mechanical polishing (CMP). By testing source/drain n+ regions isolated by two trenches, leakage current of 36.8 pA/μm was measured for a 3.3 V on drain. It is evident that continued experimentation with STI should be implemented with a twin well process to subdue the possible effect of punch through.

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