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Investigations of the polysilicon etch process utilized by the RIT factory for CMOS fabrication were conducted. The RIT factory process utilizes a dry polysilicon etch process that employs SF6 and o2 chemistry, with flow rates of 42 sccm and 7.5 sccm, at 400 mTorr pressure and 40 watts of RF power in a GEC PlasmaCell. This process was found to suffer from uniformity problems. Stdies were done to attempt to improve the etch uniformity, by varying the chamber pressure. A significant improvement in the uniformity was achieved for a much lower chamber pressure of 175 mTorr under the same conditions of power and flow rates. Results consisting of etch rate, linewidth loss, sidewall angle and selectivity with regards to silicon dioxide have been included in this paper.

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