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This project was an investigation into transistor development in areas of implanted wells and source/drain regions. Wafer processing was put through the existing RIT PMOS process, but incorporated two areas of comparison: ion implantation of an n-type well, versus the use of an n-type substrate; and doping the p-type source/drain regions by implantation, versus solid diffusion sources. Experimental results for sheet resistance and junction depth were within ten percent of those predicted by SUPREM. Electrical testing results yielded no functional transistors. Diagnostics using diffused and implanted resistors in the wells indicated that the wells were too shallow to properly isolate these devices fabricated with this process.

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