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Publication Date

1988

Document Type

Paper

Abstract

Currently, the Integrated Circuit Editor (ICE), a CAD I.C. design tool used for layouts at RIT, lacks any design rule checking simulation capabilities. This project involved writing a program that would translate the output file from ICE in the CalTech Intermediate Format (CIF) into a format that would be readable by other software tools, such as design rule checking and circuit node extraction programs.

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