Jessica Marks

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This paper presents the development, fabrication, and testing of a new 6” Metal Gate PMOS process. The new 6-inch Metal Gate PMOS process is an upgrade from the 4-inch Metal Gate PMOS process, which is the process currently used at RIT for the IC Technology course as ivell as the Short Course. The upgrades include the use of 6-inch wafers from 4-inch wafers, four levels per mask lithography instead of one level per mask lithography, ion implant instead of spin on dopant, and the number of control wafers was reduced from five wafers to three wafers. Development and fabrication of the 6-inch Metal Gate PMOS process are discussed, as well as the testing of the devices on the chip. The overall process was determined to be successful, yielding working devices, and is suitable to be used in the future with the IC Technology course and the Short Course.

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