Garret Phillips

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MEMs devices at RIT utilize off chip circuitry to be properly utilized. This paper purposes an eight bit successive approximation analog to digital converter (ADC) to add to said devices as to simplify their operation. The ADC was designed and simulated using Mentor Graphics and Winspice software for the digital and analog components respectively. Lay out was then performed for the device as well as a simplified three bit version and various test circuits. Fabrication was done in the RIT SFML using RIT’s Sub-μ CMOS process, which uses a 2μm gate length. Functional transistors and simple devices were realized. It was found that any device relying on Metal 2 did not work as desired as misprocessing post Via 1 etch left a 34nm barrier layer between the Metal 1 and Via 1 layer.

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