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Given a cross-section and functionality requirements for a photodiode designed for application as the focal plane array on SNAP (SuperNova Acceleration Probe), a proposed satellite in the Joint Dark Energy Mission by NASA and the DOE, a process has been developed to fabricate the device in the most efficient and reliable manner. The photodector is to be hybridized with a ROIC (Read-Out Integrated Circuit) that interprets the individual pixel signals and converts the electrical information into an image. After several versions of the process based on simulations, efficiency of sequence, and research, a test run of key process steps was completed to evaluate chosen process values and their final results, including well profile and I-V characteristics. The results from the test run were used to create a preliminary process flow for device wafer fabrication. The process was implemented in full on a small lot of device wafers with some monitor wafers, with the entire process (not including test) requiring about 100 hours. The results from this device run were used to create a new revised version of the process flow in order to attain better functionality from the device. After this device run was completed, the results were analyzed and used to update the process flow again to address deficiencies in the resulting devices and processing difficulties.

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