In the world of optoelectronics a common barrier has been integrating logic and device circuits on a single substrate, as it was generally only possible to optimize the device for the logic, or the optoelectronic device at hand. However, a new approach that uses metal organic chemical vapor deposition (MOCVD) enables the growth of Ill-V semiconductors on silicon substrates. The fact that 111-V semiconductors can now be integrated within the current silicon CMOS processes may allow new possibilities. An approach to investigate the feasibility of this process has been investigated. The enabler to integrate HI-V is an innovative approach called aspect ratio trapping (ART) developed by Amberwave. This method involves the use of oxide trenches to trap defects in a buffer region during crystal growth (Figure 1). The growth process is a selective growth that only occurs on silicon and this process. ART on Ill-V’s only works well with a ratio greater than 2:1 for oxide thickness to patterned oxide opening. The objective of this project is to develop a process to build these structures at HIT, perform a growth in Amberwave’s reactor, and then characterize the film. In the future, HIT may also become involved in the Chemical mechanical planarization (CMP) process for these structures. A mask was designed with four different pitches to characterize different density of features (fig. 5). Text labels were also added on the mask so that one could optically determine the pitch and in addition the reticle had labels that describe the relative field position to be used for CMP characterization. In order to be able to pattern the submicron features with a positive tone resist, a bottom antireflective coating (BARC) donated by Brewer Science was used to increase the process window in which a useable image was present. The thickness of this layer was tuned specifically to minimize the substrate reflection. By optimizing film thickness parameters and setting the focus near the bottom of the resist, this yielded much greater process latitude. After this the patterns were etched using the P5000’s magnetically enhanced etch chamber, the etched features were imaged a new Zeiss SEM at University of Rochester and the 3:1 etched features yielded acceptable profiles (fig. 10). In order to prepare patterned wafers here at HIT, the level of contamination in the process and toolset at HIT must to be characterized. The main concern is to not contaminate the growth chamber that Amberwave will be using to perform the growth of the semiconductor materials. A method of metals analysis called vapor phase decomposition-inductively-coupled plasma mass spectrometry (VPD ICP MS) was utilized as a surface contamination metric. After sending the samples to ChemTrace, it was determined that an RCA would dramatically reduce the surface contaminates present on the wafer to acceptable levels for the MOCVD reactor (fig. 6). Interesting future projects include building and characterizing a GaAs laser. Another appealing project involves building silicon drive transistors connecting them to GaAs tunneling or memory devices. It was shown that the pattern transfer portion is indeed possible at HIT and this project has set the stage for future projects regarding aspect ratio trapping.
"Deep Submicron Pattern Formation for Selective Epitaxial Growth of II-V Semiconductors,"
Journal of the Microelectronic Engineering Conference: Vol. 17:
1, Article 4.
Available at: https://repository.rit.edu/ritamec/vol17/iss1/4