A process for forming Esaki Diodes in Germanium bulk material was characterized. In doing so its processing characteristics were studied to determine whether it could be transferred into Aspect Ratio Trapping, ART, material. It was determined that transfer was feasible with the optimization of the spin on dopant process and strict control of the wet etching of the spin on dopant and Aluminum. Following process characterization electrical data was collected for a range of devices with varying process parameters. The maximum peak to valley current ratio was 1.5 and maximum peak current density was 5kA/cm2. The PVCR value was very close to data collected by a group at Notre Dame who’s process was the basis for the one used in this project4. However, the maximum peak current density was much lower, most likely due the decreased dopant concentration of the spin on dopant. Upon completion of the project a process, which could be transferred to ART, was obtained and baseline data was collected for comparison to future devices.
Sieg, Stuart A.
"Process Characterization for Integration of Esaki Diodes into Aspect Ratio Trapping Material,"
Journal of the Microelectronic Engineering Conference: Vol. 17:
1, Article 17.
Available at: https://repository.rit.edu/ritamec/vol17/iss1/17