The design and fabrication of a two-level subtractive aluminum metal backend was completed at the Rochester Institute of Technology. Metall-Metal2 (M1-M2) via chains were used as electrical test structures and tested operational. The optimal process uses 4000A of LTO for an ILD, a non-heated metal2 aluminum sputter deposition, and a chlorine-based plasma for metal etch. Resistance measurements taken through via chains produced values of —400Ω. While an ideal aluminum bar of the via chain’s dimensions should have a resistance of —100Ω, a contact resistance exists at each via throughout the chain and increases the resistance value. Capacitors were also electrically tested to determine ILD effectiveness. A 200 μm x 200 μm M1-ILD-M2 capacitor has a theoretical value of 3.5pF and the measured structures ranged from 3.01pF to 3.45pF. In addition to demonstrating that the first and second level metal lines could make electrical contact through via openings, testing was done to ensure electrical separation existed when needed. Metal2 lines overlapping metall lines were tested and measured to be electrically isolated, shown in Figures 4-6. This process has created a bilayer metallization design that allows for multilevel aluminum connections and electrical isolation where needed and can be readily implemented in RIT’s present CMOS.
"Development of a Bilayer Metallization for RIT's Existing CMOS Process,"
Journal of the Microelectronic Engineering Conference: Vol. 16:
1, Article 1.
Available at: https://repository.rit.edu/ritamec/vol16/iss1/1