Patrick Warner

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The goal of this project was to design a process to form a PIN structure on silicon on insulator (SOl) wafers, IBIS donated the wafers for this project. Using a combination of standard and novel wafer processing techniques allowed for successful completion of the device. These techniques involved a four-layer mask process that utilized both state of the art and older tool sets. A methodology for lithographic processing of wafer pieces has been expanded upon and documented for future use.

Testing demonstrated resistor like behavior opposed to the expected diode behavior. This result is indicative of a short through the device. The observed undercutting of the buried oxide is the most likely culprit. Undercutting would allow the surface silicon to come in contact with the bulk silicon creating an electrical path around the intrinsic region of the device.

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