A nickel silicidation process has been developed for the Semiconductor & Microsystems Fabrication Laboratory (SM FL) at Rochester Institute of Technology (RIT). NISI and Ni2Si were obtained in doped source/drain and polysilicon gate regions respectively at rapid thermal annealing (RTA) condition of 500°C for 60 seconds. The sheet resistance of nickel silicide in both regions was measured to be 0.45Ω/o — 0.5Ω/o. Nickel silicide was also integrated into an RIT NMOSFET process where silicide was formed over the S/D and polysilicon gate regions. Rutherford Backscatter and x-ray diffraction data showed the formation of NiSi phase in the S/D region and Ni2Si in the polysilicon region. Preliminary electrical data from N1Si SID NMOS showed an increase in drain current by about 1.5 orders of magnitude, an increase in threshold current by 1 order of magnitude, a decrease in threshold voltage by 1/2 , and significantly better gate control.
"Integration of Nickel Monosilicide (NiSi) into an RIT SMFL NMOS Device,"
Journal of the Microelectronic Engineering Conference: Vol. 15:
1, Article 12.
Available at: https://repository.rit.edu/ritamec/vol15/iss1/12