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The goal of this investigation was to ascertain a viable low temperature gate dielectric for an emerging TFT fabrication process at RIT. Various candidates were investigated to find the best solution for a low temperature gate dielectric. Materials studied include low temperature oxide (LTO) using low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) silicon nitride, and PECVD Tetra Ethyl Ortho Silicate (TEOS). Capacitors were fabricated with these materials, as well as a standard thermal oxide as a control. Wafers were examined both with and without anneals at 600°C in order to study bulk oxide and interface charge levels. Surface Charge Analysis (SCA) and C-V curves were generated in order to analyze and compare charge levels of the various treatment combinations.

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