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Publication Date

2003

Document Type

Paper

Abstract

This project serves as a study to determine the feasibility of the current CMOS toolsets and processes available at Semiconductor & Microsystems Fabrication Laboratory (SMFL) for the fabrication of whole wafer power devices. Several designs and devices were explored. The Insulated Gate Bipolar Transistor (~LGBT) is a device widely used for high power electronic applications and was selected for this study. This device has bipolar current flow and a MOS gate thus combining advantages of both the Double diffused MOS (DMOS) and Power Bipolar junction transistor. Prototypes consisting of transistors with varying densities, gate lengths and gate widths were fabricated to characterize these devices Attempts were made to study the effect of field oxide thickness on breakdown voltage. Photomask were designed in mentor graphics. Process was designed to obtain required power rating. The desIgn was simulated in ATHENA to verify the process conditions. The IGBTs were fabricated as per the design on standard 4” high resistivity n-type wafers. 8 device wafers and 4 control wafers were used for the process, which involved 4 mask levels. Two additional wafers were processed with this lot to obtain DMOS. The fabricated devices were tested to determine electrical characteristics. The IV characteristics obtained for both the DMOS and IGBT exhibit field effect. However this field effect is in parallel with a parasitic conductance and limits the transistor from turning off. It is also observed that the devices are operational as depletion mode devices instead of enhancement mode devices. The shortcomings of the current process and device designed have been listed and required modifications have been suggested.

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