Steven D. Kirby

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A Fin Field Effect Transistor (FinFET) is one of several novel devices that may be used in the future to minimize short channel effects. The FinFET is fabricated on silicon on insulator (SOI) substrate and uses basic integrated circuit processing techniques to obtain a double gate structure. The double gate structure helps to improve subthreshold characteristics and provides low leakage current. The objective of this project was to improve the FinFET device built at RIT. Functioning FinFETs were designed and fabricated previously at RIT. The new design and process changes will help in the understanding of issues found in previous test results. The design includes FInFET structures, fin resistors to determine series resistance, and contact structures. The process flow was based on the flow used previously at RIT. One processing change is the use of rapid thermal anneal (RTA) as opposed to furnace anneals. The fabrication of FinFETs was completed. The testing showed that there was a contact resistance issue along with a high shunt conductance. The resulting threshold voltage was approximately IV. There was no obvious difference in the threshold voltage or saturation current between the planar and FinFET devices.

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