In this investigation, efforts have been made to move the Microelectronic Engineering Program at Rochester Institute of Technology to the next technology node by developing and fabricating a 0.5μm PMOS process. Currently, RIT is fabricating 1.0μm CMOS devices. A successful 0.5μm PMOS process can be incorporated into a full flow 0.5μm CMOS process. Both process and electrical simulations were done in order to predict performance. Key process features include blanket n-well, LOCOS isolation, 15nm gate oxide, i-line lithography, self-aligned source and drain, P+ doped polysilicon gates, and shallow source and drains. A test chip was created and the fabrication process was completed. The process was unable to produce working devices. The failure mode is residual oxide in the contacts to the polysilicon gates.
Camp, Lisa M.
"Moving RIT to Submicron Technology: Fabrication of 0.5μm P-Channel MOS Transistors,"
Journal of the Microelectronic Engineering Conference: Vol. 13:
1, Article 3.
Available at: https://repository.rit.edu/ritamec/vol13/iss1/3