With the ever-decreasing size of device geometries today, all aspects of processing must allow for proper scaling of device parameters including junction depths. Currently in industry this challenge is met with ultra-low-energy ion implants combined with rapid thermal annealing to create the necessary profiles. It is also important to have good uniformity and throughput in order for the process to be acceptable in a manufacturing environment. Since the installation of RIT’s Varian 350D last year, there have been no implants performed at less than 3OKeV. In order to develop future processes for the student-run factory and open research possibilities, ion implants of Arsenic, Phosphorus, and BF2 were performed at 10, 15, and 2OKeV in drift mode into 6” wafers covered with a thin screen oxide. Implant simulations and sheet resistance uniformity along with other information were examined to investigate the 350D’s capabilities.
Miga, Brian J.
"Low Energy Ion Implant Capabilities at RIT,"
Journal of the Microelectronic Engineering Conference: Vol. 12:
1, Article 14.
Available at: https://repository.rit.edu/ritamec/vol12/iss1/14