Copper Gate MOS Capacitors Utilizing Chemical-Mechanical Planarization

Authors

Luc Dupre

Publication Date

2002

Document Type

Paper

Abstract

Applying chemical mechanical planarization techniques to form the gate for a Cu/Ti/SiO₂/Si capacitor stack has shown to be a viable alternative to conventional etching techniques used in the fabrication of MOS devices. Furthermore, it is reported that CMP does not compromise the integrity of the dielectric nor does it have an adverse affect on device performance.

Recommended Citation

Dupre, Luc (2002) "Copper Gate MOS Capacitors Utilizing Chemical-Mechanical Planarization," Journal of the Microelectronic Engineering Conference: Vol. 12: Iss. 1, Article 11.
Available at: https://repository.rit.edu/ritamec/vol12/iss1/11