Desgin of an Ion Implantation Process Monitoring Chip on I.C.E and Provide a Methodology for Evaluation of Testing Results

Authors

Joseph J. Burkis

Publication Date

1987

Document Type

Paper

Abstract

A test chip has been designed for experimental use in determining and maintaing the operation of an ion implanter. The structures on this chip provide information on the implant processing and post implant annealing. Implant does will be monitored using van der PAUW [1] structures, implanted resistors and comparison of threshold adjusted MOSFET with adjacent non adjusted MOSFET. Surface effects and annealing information will be taken from analysis of gated diodes [2].

Recommended Citation

Burkis, Joseph J. (1987) "Desgin of an Ion Implantation Process Monitoring Chip on I.C.E and Provide a Methodology for Evaluation of Testing Results," Journal of the Microelectronic Engineering Conference: Vol. 1: Iss. 1, Article 5.
Available at: https://repository.rit.edu/ritamec/vol1/iss1/5