The design of a five micron, polysilicon gate, CMOS process is discussed. A p-well approach was used with aoriented n-type substrate as the starting material. Calculations of the threshold adjustment dose and desired doping level of the p-well were based on a desired threshold voltage of -0.8 volts for the p-channel transistor and 0.8 volts for the n-channel device. The desired doping levels of the sources and drains were based on minimizing the parasitic resistances and capacitances associated with a MOS transistor. SUPREM II was used to determine the implant/drive cycles necessary to obtain the required doping profiles and to simulate the oxide growths, sheet resistances, and junction depths of the various levels. Simulation of the electrical characteristics of the NOMOS and PMOS devices and the CMOS inverter was done using SPICE.
Scoopo, John P.
"A Five Micron, Self Aligned, Polysilicon Gate CMOS Process Design,"
Journal of the Microelectronic Engineering Conference: Vol. 1:
1, Article 28.
Available at: https://repository.rit.edu/ritamec/vol1/iss1/28