Abstract

As the number of bus masters increases in chip, the performance of a system largely depends on the arbitration scheme. The throughput of the system is affected by the arbiter circuit which controls the grant for various requestors. An arbitration scheme is usually chosen based on the application. A memory arbiter decides which CPU will get access for each cycle. A packet switch uses an arbiter to decide which input packet will be scheduled to the output. This paper introduces a Round-robin arbitration with adjustable weight of resource access time. The Round-robin arbiter mechanism is useful when no starvation of grants is allowed. The arbiter quantizes time shares each requestor is allowed to have. A minimal fairness is guaranteed by granting requestors in Round-robin manner. The requestors can prioritize their time shares by the weight. For example, if requestor A has a weight of two and requestor B has a weight of four, arbiter will allocate requestor B with time slice two times longer than that of requestor A’s. The verification of the design is carried out using SystemVerilog. The inputs of the arbiter are randomized, outputs are predicted in a software model and verification coverage is collected. The work in this paper includes design and verification of a weighted Round-robin arbiter.

Publication Date

8-2018

Document Type

Master's Project

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Mark A. Indovina

Advisor/Committee Member

Sohail A. Dianat

Campus

RIT – Main Campus

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