Abstract
One of the indispensable aspects of digital image processing is the requirement of varied image resolutions. To achieve varied resolution, scaling comes into picture. Two important applications of scaling is good pictorial quality for human interpretation and processing of digital images for storage, transmission and for representation of autonomous machine perception. This paper focuses on the transmission application. The size of the image if reduced occupies less space in the communication medium thus reducing the bandwidth requirement. And also the server space and the processing power of the image is reduced greatly. The standard for digital television transmission over terrestrial, cable and satellite networks is defined by Advanced Television Systems Committee (ATSC), with either 704 × 480 or 640 × 480 pixel resolutions, at 24, 30, or 60 progressive frames per second. This paper proposes a monochrome and colored image down scaling core with memory banks for accessing the image pixels. A 704 x 480 pixel resolution image was used. The core has minimum complexity and was developed in Hardware Descriptive Language (HDL). Its been benchmarked in various ASIC technologies.
Publication Date
12-2017
Document Type
Master's Project
Student Type
Graduate
Degree Name
Electrical Engineering (MS)
Department, Program, or Center
Electrical Engineering (KGCOE)
Advisor
Mark A. Indovina
Advisor/Committee Member
Sohail A. Dianat
Recommended Citation
Parthipan, Vaishnavi, "Image Down-Scaler Using the Box Filter Algorithm" (2017). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/9704
Campus
RIT – Main Campus