Abstract

Integrated circuits and microprocessor chips have become integral part of our everyday life to such an extent that it is difficult to imagine a system related to consumer electronics, health care, public transportation, household application without these small components. The heart of these circuits is, the metal oxide field-effect transistor (MOSFET) which is used as a switch. The dimensions of these transistors have been scaled from a few micrometers to few tens of nanometer to achieve higher performance, lower power consumption and low cost of production. According to the International Technology Roadmap for Semiconductors (ITRS), beyond 32 nm technology node, planer devices will not be able to fulfill the strict leakage requirement anymore due to overpowering short channel effects and need of multi-gate transistor is inevitable. The motivation of the thesis therefore is to investigate techniques to engineer threshold voltage of a tri-gate FinFET for low power and ultra-low power applications. The complexity of physics involved in 3D nano- devices encourages use of advanced simulation tools. Thus, Technology Computer Aided Design Tools (TCAD) are needed to perform device optimization and support device and process integration engineers. Below 20nm technology node, the Fin-shaped Field Effect Transistor or Tri-gate transistor requires extensive use of 3D TCAD simulations.

The multi-gate devices such as FinFETs are considered to be one of the most promising devices for Ultra Large Scale Integration (ULSI). This device structural design with additional gate electrodes and channel surfaces offers dynamic threshold voltage control. In addition, it can provide better short channel performance and reduced leakage. In this study, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (50pA/μm

Library of Congress Subject Headings

Metal oxide semiconductor field-effect transistors--Design and construction; Integrated circuits--Very large scale integration; Nanoelectronics

Publication Date

5-2017

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Santosh Kurinec

Advisor/Committee Member

Karl Hirschman

Advisor/Committee Member

Robert Pearson

Comments

Physical copy available from RIT's Wallace Library at TK7871.95 .W35 2017

Campus

RIT – Main Campus

Plan Codes

MCEE-MS

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