Abstract

The performance of Indium Gallium Zinc Oxide (IGZO) Thin-Film Transistors (TFTs) has improved significantly in recent years; however, device stability still remains a significant issue. In bottom-gate TFTs a difficult challenge is the lack of gate control on the back-channel region, resulting in distortion in ID - VGS characteristics. In this work a bottom-gate TFT process was established using SiO2 as a back-channel passivation layer. The process was modified with options to implement TG (TG) and Double-Gate (DG) configurations. TFTs were fabricated utilizing a SiO2 layer deposited shortly after the IGZO sputter process, followed by an oxidizing ambient anneal treatment. The process supports a low-defect IGZO interface, with TG and DG configurations demonstrating improvements in channel control compared to a traditional bottom-gate TFT. Electrical characteristics from each process treatment and gate configuration where then compared. A SPICE level 2 compatible IGZO TFT model was developed, with extracted parameter values providing a quantitative measure of device operation. Measured characteristics were also used to develop arerefined material and device model for TCAD simulation.

Library of Congress Subject Headings

Thin film transistors--Materials; Thin film transistors--Design and construction; Integrated circuits--Passivation

Publication Date

8-30-2016

Document Type

Thesis

Student Type

Graduate

Degree Name

Microelectronic Engineering (MS)

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Karl Hirschman

Advisor/Committee Member

Sean Rommel

Advisor/Committee Member

Michael Pierce

Comments

Physical copy available from RIT's Wallace Library at TK7871.96.T45 E49 2016

Campus

RIT – Main Campus

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