Abstract
Face detection has primarily been a software-based effort. A hardware-based approach can provide significant speed-up over its software counterpart. Advances in transistor technology have made it possible to produce larger and faster FPGAs at more affordable prices. Through VHDL and synthesis tools it is possible to rapidly develop a hardware-based solution to face detection on an FPGA.
This work analyzes and compares the performance of a feature-invariant face detection method implemented in software and an FPGA. The primary components of the face detector were a Bayesian classifier used to segment the image into skin and nonskin pixels, and a direct least square elliptical fitting technique to determine if the skin region's shape has elliptical characteristics similar to a face. The C++ implementation was benchmarked on several high performance workstations, while the VHDL implementation was synthesized for FPGAs from several Xilinx product lines.
The face detector used to compare software and hardware performance had a modest correct detection rate of 48.6% and a false alarm rate of 29.7%. The elliptical-shape of the region was determined to be an inaccurate approach for filtering out non-face skin regions. The software-based face detector was capable of detecting faces within images of approximately 378x567 pixels or less at 20 frames per second on Pentium 4 and Pentium D systems. The FPGA-based implementation was capable of faster detection speeds; a speedup of 3.33 was seen on a Spartan 3 and 4.52 on a Virtex 4. The comparison shows that an FPGA-based face detector could provide a significant increase in computational speed.
Library of Congress Subject Headings
Human face recognition (Computer science); Pattern recognition systems; Computer vision; Field programmable gate arrays
Publication Date
3-2006
Document Type
Thesis
Student Type
Graduate
Degree Name
Computer Engineering (MS)
Department, Program, or Center
Computer Engineering (KGCOE)
Advisor
Juan Cockburn
Advisor/Committee Member
Andreas Savakis
Advisor/Committee Member
Marcin Lukowiak
Recommended Citation
Rericha, Christopher J., "FPGA implementation and performance comparison of a Bayesian face detection system" (2006). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/8187
Campus
RIT – Main Campus
Comments
Physical copy available from RIT's Wallace Library at TA1650 .R47 2006