Abstract

Methods of communication and dissemination of information have changed dramatically with the emergence of the Internet and mobile phones. To sustain this revolution, we need reliable mass storage devices which would store information not only in large amount in small space but also for long time. Therefore, realizing high performance memory technologies is very critical for this revolution. This work contributes towards the development of one such technology; Magnetic Random Access Memory (MRAM) based on Magnetic Tunnel Junction (MTJ). The research conducted in this study is primarily focused on the process development for integrating MTJ on silicon. The film stack explored in this work is CoFeB/MgO-based. The relevant issues in this integration such as smooth bottom electrode preparation, low thermal budget, process chemistry and parameters, and MTJ patterning involving ion-milling have been addressed in this work. Ta and NiCr are evaluated as candidates for bottom electrode. Spin-on Glass (SOG)-based low temperature Inter Level Dielectric (ILD) process is developed. MTJ devices with varying sizes with four terminal contacts for on wafer testing have been designed and fabricated using the process developed. The devices exhibited Resistance-Area (RA) product in the range of 1-5 k_Um2. Recent literature on MgO-based MTJ devices has reported values in a range of 0.1 – 1000 k_um2. This data confirms the electrical integrity of the MTJ fabricated. The RA values have been observed to be unchanged on application of magnetic field (+-300Oe). Detailed investigations have been carried out to find possible causes for the absence of magnetic response from these junctions. These include XRD analysis of the MTJ stack for CoFeB crystallization and STEM-PEELS studies to investigate the chemical composition. “Neel coupling” or “Orange peel coupling” due to interface roughness is thought to be one of the main possible causes for magnetically inactive junctions. Suggestions for future are given on the basis of the results from the process and the experiments. In summary, a process has been developed for fabricating MTJ on silicon yielding desired values for junction resistivity. The magnetic response is extremely sensitive to film roughness at nanoscales and will require control of roughness at each step starting with wafer specification. It is concluded that with a control of surface roughness and recommended modifications in MTJ films, a CMOS compatible process for fabricating MTJ is plausible at RIT. (Refer to PDF file for exact formulas)

Library of Congress Subject Headings

Integrated circuits--Very large scale integration--Design; Random access memory; Tunneling (Physics); Magnetization

Publication Date

2007

Document Type

Thesis

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Kurinec, Santosh - Chair

Advisor/Committee Member

Rommel, Sean

Advisor/Committee Member

Moon, James

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7874.75 .P36 2007

Campus

RIT – Main Campus

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