Andrew McCabe

Abstract

Gate-Induced drain leakage (GIDL) is an unwanted short-channel effect that occurs at higher drain biases in an overdriven off state of a transistor. The GIDL is the result of a deep depletion region that forms in the drain at high drain-to-gate biases. The depletion region causes significant band bending which in-turn allows conductive band-to-band tunneling creating excess current. In a PFET, electrons tunnel from the drain to the body while holes tunnel into the drain. By utilizing the effects of high energy, or "hot", electrons, the GIDL current in an accumulation-mode PFET can be suppressed. This suppression is thought to be due to local creation of interface charge at the gate-oxide/silicon interface located close to the drain end of the transistor. This charge in-turn creates a mirror charge in the silicon, which acts like a pseudo-asymmetrical lightly-doped drain structure. Up until now, this effect has only been demonstrated on the first order. The goal of this study is to further investigate the effects of high-field stress on the suppression of GIDL in accumulation- mode PFETs. An overview of background information, simulations, fabrication, electrical characterization, and physical characterization are presented in this study.

Library of Congress Subject Headings

Thin film transistors--Design and construction; Electric leakage--Prevention

Publication Date

2010

Document Type

Thesis

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Hirschman, Karl

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.96.T45 M32 2010

Campus

RIT – Main Campus

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