Abstract

Designing a digital system that implements an assortment of specialized high performance algorithms can be costly. Considerable non-recurring engineering costs are required to develop an application specific integrated circuit (ASIC). Additionally, updating or adding features to a design requires the ASIC to be redesigned and refabricated. An alternative to using an ASIC is the field programmable gate array (FPGA). The modern FPGA's ability to be partially reconfigured at runtime allows for the device to have the flexibility normally associated with a processor, while also being able to implement digital logic like in an ASIC. This capability allows for multiple digital functions to be loaded into the device at runtime only as needed. This thesis focuses on developing a reconfigurable framework that enables stream-oriented applications to make more effective use of FPGA resources and to manage partial reconfiguration operations across multiple tasks. This multichannel framework addresses several shortcomings of past research that evaluated various dynamic partial reconfiguration techniques using a color space conversion (CSC) engine. This framework allows for multiple different computations to be performed simultaneously, further improving throughput and flexibility of applications implemented within it. Performance of the system is evaluated by comparing its computational throughput to previous efforts using the CSC engine as well as the performance gained from the flexible scheduling that the framework allows. Implementations using the CSC engine show that performance can be improved up to 5 times faster than previous works, as a result of exploiting parallelism.

Library of Congress Subject Headings

Field programmable gate arrays--Design and construction; Image processing--Digital techniques; Programmable array logic

Publication Date

2012

Document Type

Thesis

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Patru, Dorin

Advisor/Committee Member

Lukowiak, Marcin

Advisor/Committee Member

Shaaban, Muhammad

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7895.G36 M95 2012

Campus

RIT – Main Campus

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