Abstract

CMOS scaling is currently facing a technological barrier. Novel technologies are being proposed to keep up with the need for computation power and speed. One of the proposed ideas is the quantum-dot cellular automata (QCA) technology. QCA uses quantum mechanical effects in the device at the molecular scale. QCA systems have the potential for low power, high density, and regularity. This thesis studies QCA devices and uses those devices to build a simple field programmable gate array (FPGA). The FPGA is a combination of multiple configure logical blocks (CLBs) tiled together. Most previous work on this area has focused on fixed logic and programmable interconnect. In contrast, the work at the Rochester Institute of Technology (RIT) has designed and simulated a configurable logic block (CLB) based on look-up tables (LUTs). This thesis presents a simple FPGA that consists of multiple copies of the CLB created by the RIT group. The FPGA is configured to emulate a ripple-carry adder and a bit-serial multiplier. The latency and throughput of both functions are analyzed. We employ a multilevel approach to design specification and simulation. QCADesigner software is used for layout and simulation of an individual CLB. For the FPGA, the high-level HDLQ Verilog library is used. This hybrid approach provides a high degree of confidence in reasonable simulation time.

Library of Congress Subject Headings

Quantum dots; Cellular automata; Field programmable gate arrays

Publication Date

2010

Document Type

Thesis

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Peskin, Eric

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7874.88 .T86 2010

Campus

RIT – Main Campus

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