Abstract

A fully depleted silicon p-i-n image sensor for a very low noise hybrid CMOS imaging system was simulated, fabricated, and electrically characterized. The image sensor was then bonded to the foundry fabricated CMOS circuitry to create the imaging system. SILVACO Atlas was used to simulate the steady state electrical operation of the device as well as the optical response. Revisions were made to an existing mask set to allow the use of both contact and projection lithography in the fabrication process. Significant process improvements were introduced to eliminate needless complexity and reduce leakage current from the previously reported 1.5x10-6 A/cm2 below the goal of 2.2x10-9 A/cm2. Following fabrication of the image sensors, electrical testing was performed to verify diode quality from leakage and lifetime measurements. A lift-off process was developed for thick metal layers used in the bump-bond hybridization process. Daisy-chain test parts were created to characterize the mechanical and electrical connections formed in the hybridization process. Fabricated p-i-n photodiode arrays were diced and hybridized to read-out integrated circuits using a flip-chip bump bond process with indium interconnects. Testing of hybridized devices is currently ongoing.

Library of Congress Subject Headings

Optical detectors--Design and construction; Silicon diodes--Design and construction; Metal oxide semiconductors, Complementary; Imaging systems

Publication Date

2012

Document Type

Thesis

Department, Program, or Center

Microelectronic Engineering (KGCOE)

Advisor

Hirschman, Karl

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.99.M44 S43 2012

Campus

RIT – Main Campus

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