Xiang Li

Abstract

This thesis presents a high performance novel VLSI architecture of a H.264 motion estimator, which can be used as a building block for real-time H.264 video compression. Full-search block matching algorithm was used in this design. Pipeline structure was developed for variable block size processing units to work in parallel. The speed at 125MHz is good for real time motion estimation with 25/sec frame rate and 640x480 resolutions. The processing speed is also independent of the threshold level of Sum of Absolute Difference (SAD), which is used to determine the size of the macro block. The architecture is implemented with Register Transfer Level VHDL codes then synthesized with Synopsys Design Compiler, using TSMC 0.25um technology. The synthesized Application Specific Integrated Circuits (ASIC's) has an area of 664um x 664um.

Library of Congress Subject Headings

Video compression--Standards; Digital video--Standards; Integrated circuits--Very large scale integration; Pipelining (Electronics)

Publication Date

2004

Document Type

Thesis

Student Type

Graduate

Degree Name

Electrical Engineering (MS)

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Kenneth Hsu

Advisor/Committee Member

Pratapa Reddy

Advisor/Committee Member

Dorin Patru

Comments

Physical copy available from RIT's Wallace Library at TK6680.5 .L5 2004

Campus

RIT – Main Campus

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