Abstract
A new orientation to the conventional MOSFET is proposed. Processing issues, as well as short channel effects have been making planar MOSFET scaling increasingly difficult. It is predicted by the 2001 International Technology Roadmap for Semiconductors (ITRS) that non-planar devices will be needed for production as early as 2007. The device proposed in this thesis is similar in operation to the planar MOSFET, however the current transport from source to drain, normally in the same plane as the wafer surface, is oriented perpendicular to the die surface. The proposed device has successfully been simulated, showing a proof of concept. Fabrication of the proposed devices led to the creation of vertical MOS Gated Tunnel Diodes. This work, in fact, represents possibly the first demonstration of this type of technology. Suggestions are made to improve upon the proposed vertical MOSFET as well as the vertical MOS Gated Tunnel Diode.
Library of Congress Subject Headings
Metal oxide semiconductors, Vertical; Metal oxide semiconductor field-effect transistors
Publication Date
2003
Document Type
Thesis
Student Type
Graduate
Degree Name
Microelectronic Engineering (MS)
Department, Program, or Center
Microelectronic Engineering (KGCOE)
Advisor
Sean Rommel
Advisor/Committee Member
Santosh Kurinec
Advisor/Committee Member
Karl Hirschman
Recommended Citation
Tabakman, Keith H., "Concept, design, simulation, and fabrication of an ultra-scalable vertical MOSFET" (2003). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/7062
Campus
RIT – Main Campus
Comments
Physical copy available from RIT's Wallace Library at Tk7871.99.M44 T23 2003