Author

Gu-Ching Lin

Abstract

Twenty to fifty percent of the active area of most semicustom integrated circuits is devoted to combinational logic. Automating the synthesis and optimization of combinational circuitry can result in significant improvements in both the design cycle time and the overall area of the implementation. This thesis presents a rule-based system that optimizes combinational logic for a given technology. By performing Boolean function minimization, decomposition, logic synthesis and a series of local transformations4, the system achieves area reductions and saves valuable design time.

Library of Congress Subject Headings

Expert systems (Computer science)--Design; Conbinatory logic

Publication Date

2-5-1987

Document Type

Thesis

Student Type

Graduate

Degree Name

Computer Science (MS)

Department, Program, or Center

Computer Science (GCCIS)

Advisor

John Ellis

Advisor/Committee Member

John Biles

Advisor/Committee Member

George Brown

Comments

Physical copy available from RIT's Wallace Library at QA76.76.E95 L56 1987

Campus

RIT – Main Campus

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