Abstract

A modular 2-micron BiCMOS process was developed from an existing 2-micron N-Well CMOS process. The process maintains compatibility with the existing 2- micron CMOS design rules and design library, meets the NPN device parameter targets supplied, and utilizes present manufacturing operations and equipment, with a minimum number of additional masks and steps. NPN transistor parameter targets were determined from intended technology applications. Process integration options are introduced and evaluated. A procedure for process latitude determination and process optimization is presented.

Library of Congress Subject Headings

Metal oxide semiconductors, Complementary; Bipolar integrated circuits

Publication Date

11-1-1991

Document Type

Thesis

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Zentum, Reyan

Advisor/Committee Member

Fuller, Lynn

Advisor/Committee Member

Pearson, Robert

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7871.99.M44G84 1991

Campus

RIT – Main Campus

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