Peter H. Sohn

Abstract

The design of a microprocessor based hybrid system for digital error correction is presented. It is shown that such a system allows for implementation of several cyclic codes at a variety of throughput rates providing variable degrees of error correction depending on current user requirements. The theoretical basis for encoding and decoding of binary BCH codes is reviewed. Design and implementation of system hardware and software are described. A method for injection of independent bit errors with controllable statistics into the system is developed, and its accuracy verified by computer simulation. This method of controllable error injection is used to test performance of the designed system. In analysis, these results demonstrate the flexibility of operation provided by the hybrid nature of the system. Finally, potential applications and modifications are presented to reinforce the wide applicability of the system described in this thesis.

Library of Congress Subject Headings

System design; Error-correcting codes (Information theory)

Publication Date

6-1-1984

Document Type

Thesis

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Rhody, Harry

Advisor/Committee Member

Riethaman, Alton

Advisor/Committee Member

Hsu, Kenneth

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: QA76.9.S88 S68 1984

Campus

RIT – Main Campus

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