Abstract
VHDL is a flexible language for programming PLDs (Programmable Logic Devices) but the way it is synthesized for different architectures varies. Since there are several types of PLDs and several synthesis tools, it is very important for the designer to know which VHDL model to use for a particular architecture in order to achieve maximum efficiency. The term efficiency refers to a good use of resources that result to a denser fit of the logic design into the PLD with a minimum implementation delay. The choice of the VHDL model also depends on the application and the expectations of the designer. Based on the information from several PLD architectures, this thesis points out the maximum efficiency models for each architecture in different aspects of VHDL programming and sequential logic applications. The architectures that the study is focused on, are the Altera MAX family and the Cypress MAX, Flash and CY7C33x families.
Library of Congress Subject Headings
Programmable logic devices; Logic design; VHDL (Computer hardware description language)
Publication Date
9-1-1995
Document Type
Thesis
Department, Program, or Center
Electrical Engineering (KGCOE)
Advisor
Name Illegible
Recommended Citation
Giannopoulos, Vassilis, "Efficient VHDL models for various PLD architectures" (1995). Thesis. Rochester Institute of Technology. Accessed from
https://repository.rit.edu/theses/5599
Campus
RIT – Main Campus
Comments
Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7872.L64G526 1995