Abstract

A novel CMOS monolithic analog multiplier capable of operating in two quadrants is described in this thesis. The multiplier incorporates a voltage-controlled variable linear resistor comprised of two FET transistors in the feedback network of an operational amplifier. This novel approach to implementing an analog multiplier results in good linearity and wide input dynamic range when compared to other implementations where an FET is incorporated in the feedback network of an operational amplifier. The analog multiplier, comprised of an operational amplifier and a variable linear resistor, has been designed. PSpice simulation results are given in support of the multiplier. Experimental results of a discrete implementation are also given. A comparison between the analytical model, the simulation results, and the experimental results is presented at the end of this thesis.

Library of Congress Subject Headings

Analog multipliers--Design and construction--Simulation methods; Linear integrated circuits--Design and construction--Simulation methods

Publication Date

5-1-1995

Document Type

Thesis

Department, Program, or Center

Electrical Engineering (KGCOE)

Advisor

Mukund, P.

Advisor/Committee Member

Fuller, Lynn

Advisor/Committee Member

Perlman, Daniel

Comments

Note: imported from RIT’s Digital Media Library running on DSpace to RIT Scholar Works. Physical copy available through RIT's The Wallace Library at: TK7872.M8 H344 1995

Campus

RIT – Main Campus

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