The design, simulation, fabrication and testing of .75um PMOS transistors is studied in this work. The process uses Direct Write Electron Beam Lithography for all lithography steps. The process is matched for the tool set at The Rochester Institute of Technology and their accompanying process hurdles. As of the beginning of this work, there had been no work done on obtaining a sub-micron transistor due to limitations in the optical lithography tools available at The Rochester Institute of Technology. A process flow that is robust, but as efficient as possible is used to obtain a working sub-micron PMOS transistor.
Library of Congress Subject Headings
Power transistors--Design; Metal oxide semiconductors--Design
Department, Program, or Center
Electrical Engineering (KGCOE)
Klare, Mark, "Sub-micron PMOS transistor using electron beam lithography" (1996). Thesis. Rochester Institute of Technology. Accessed from
RIT – Main Campus